Welcome to Jelloware Design©,
The name to trust for your hardware and software design.
Jelloware Design © is a Montreal based engineering firm, built around an extensive knowledge and working experience on Hardware & Software development.
We are a private Intellectual Property (IP) Core provider and System-on-Chip (SoC) design house.
Jelloware Design © creates reusable IP cores, verification components and models (VHDL and verilog) that meet the demanding requirements of your complex SoC (system-on-chip) FPGA or ASIC designs.
Our goal is to deliver complete design and verification services to your company. Our many years of expertise in FPGA design and verification as well as in SoC/ASIC integration will provide our customers with a complete solution for SoC projects.
- Our Expertise and specialized design tools are the key to faster time to market !
Intellectual Property (IP) Cores
Our IP Cores features :
- Optimized RTL design for both timing and ressources.
- Available as Clear, Human Readable VHDL or Verilog Source Code.
- Technology Independant - whether it be FPGA, CPLD or ASIC.
- Optimized for Targetted Technology .
- Timing Constraints Script.
- Customizable through generic configurations.
- Software wizard generation interface.
- Clear and complete documentation & specifications.
- Complete design example included.
- Jelloware© Guarantee to work.
- Flexible and broad licensing options.
Simulation Tools
- Testbenches.
- Simulation Models.
- Test Vectors.
- Simulation Environment.
Services
Let us do it for you ...
- System-on-Chip (SoC) / Micro Controller Design.
- FPGA Design (VHDL/Verilog).
- Tailor made Intellectual Property (IP) Core design.
- Efficient VHDL Testbench design.
- Practical VHDL Simulation environment.
Productivity Tools
VHDL Register Management Suite
Jelloware Register Management Suite© is one of the best way to help you save time and help shorten development time.
Our Register Management Suite© is more than a simple registor editor and generator. It allows everyone involved in your project from marketing people, engineering (hardwares and software) to test and integration specialist stay synchornized.
- Convenient and User Friendly registor Editor.
- One click generation of Error Free VHDL register component.
- Our Structural approch makes it very easy to use in both VHDL and C++ code.
- No need to modify exiting VHDL and C++ code when moving registers to a different address location.
- Altera Qsys© and IP-XACT.standard compatible.
- Geneartion of C++ register definitions files.
- Automatic Documentation generation (.DOC, .HTML, .PDF).
- Fully customizable generation of files (source or documentation) to match your coding standard and company style.
- Import and Export tools included.
- Embedded Register definition version control to help solve compatibility issue.
- Automatic Register Update Notifier (via email distribution list) .
